[PATCH v3 06/16] arm64: enable ptrauth earlier

Catalin Marinas catalin.marinas at arm.com
Thu Jan 16 08:24:14 PST 2020


On Mon, Dec 16, 2019 at 02:17:08PM +0530, Amit Daniel Kachhap wrote:
> diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
> index 5aaf1bb..c59c28f 100644
> --- a/arch/arm64/kernel/head.S
> +++ b/arch/arm64/kernel/head.S
> @@ -13,6 +13,7 @@
>  #include <linux/init.h>
>  #include <linux/irqchip/arm-gic-v3.h>
>  
> +#include <asm/alternative.h>
>  #include <asm/assembler.h>
>  #include <asm/boot.h>
>  #include <asm/ptrace.h>
> @@ -713,6 +714,7 @@ secondary_startup:
>  	 * Common entry point for secondary CPUs.
>  	 */
>  	bl	__cpu_secondary_check52bitva
> +	bl	__cpu_secondary_checkptrauth
>  	mov	x0, #ARM64_CPU_BOOT_LATE
>  	bl	__cpu_setup			// initialise processor
>  	adrp	x1, swapper_pg_dir
> @@ -831,6 +833,24 @@ __no_granule_support:
>  	early_park_cpu CPU_STUCK_REASON_NO_GRAN
>  ENDPROC(__no_granule_support)
>  
> +ENTRY(__cpu_secondary_checkptrauth)
> +#ifdef CONFIG_ARM64_PTR_AUTH
> +	/* Check if the CPU supports ptrauth */
> +	mrs	x2, id_aa64isar1_el1
> +	ubfx	x2, x2, #ID_AA64ISAR1_APA_SHIFT, #8
> +	cbnz	x2, 1f
> +alternative_if ARM64_HAS_ADDRESS_AUTH
> +	mov	x3, 1
> +alternative_else
> +	mov	x3, 0
> +alternative_endif
> +	cbz	x3, 1f
> +	/* Park the mismatched secondary CPU */
> +	early_park_cpu CPU_STUCK_REASON_NO_PTRAUTH
> +#endif
> +1:	ret
> +ENDPROC(__cpu_secondary_checkptrauth)

Do we actually need to park secondary CPUs early? Let's say a secondary
CPU doesn't have PAC, __cpu_setup won't set the corresponding SCTLR_EL1
bits and the instructions are NOPs. Wouldn't the cpufeature framework
park it later anyway?

-- 
Catalin



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