[PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core
xiaowei.bao at nxp.com
Thu Jan 9 02:20:59 PST 2020
> -----Original Message-----
> From: Kishon Vijay Abraham I <kishon at ti.com>
> Sent: 2020年1月9日 18:19
> To: Bjorn Helgaas <helgaas at kernel.org>; Gustavo Pimentel
> <gustavo.pimentel at synopsys.com>; Xiaowei Bao <xiaowei.bao at nxp.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>; Andrew Murray
> <andrew.murray at arm.com>; Murali Karicheri <m-karicheri2 at ti.com>; Jingoo
> Han <jingoohan1 at gmail.com>; linux-pci at vger.kernel.org;
> linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core
> On 12/12/19 4:16 AM, Bjorn Helgaas wrote:
> > On Wed, Dec 11, 2019 at 06:16:04PM +0530, Kishon Vijay Abraham I wrote:
> >> Existing MSI-X support in Endpoint core has limitations:
> >> 1) MSIX table (which is mapped to a BAR) is not allocated by
> >> anyone. Ideally this should be allocated by endpoint
> >> function driver.
> >> 2) Endpoint controller can choose any random BARs for MSIX
> >> table (irrespective of whether the endpoint function driver
> >> has allocated memory for it or not)
> >> In order to avoid these limitations, pci_epc_set_msix() is modified
> >> to include BAR Indicator register (BIR) configuration and MSIX table
> >> offset as arguments. This series also fixed MSIX support in dwc
> >> driver and add MSI-X support in Cadence PCIe driver.
> >> The previous version of Cadence EP MSI-X support is @ .
> >> This series is created on top of 
> >>  ->
> >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> >> 5ZRJnDmO1QfAKQostQci05%2BrJA%3D&reserved=0
> >>  ->
> >> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flore
> >> .kernel.org%2Fr%2F20191209092147.22901-1-kishon%40ti.com&dat
> >> Alan Douglas (1):
> >> PCI: cadence: Add MSI-X support to Endpoint driver
> >> Kishon Vijay Abraham I (3):
> >> PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
> >> PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table
> >> address
> >> PCI: keystone: Add AM654 PCIe Endpoint to raise MSIX interrupt
> > Trivial nits:
> > - There's a mix of "MSI-X" and "MSIX" in the subjects, commit logs,
> > and comments. I prefer "MSI-X" to match usage in the spec.
> > - "Fixes:" tags need not include "commit". It doesn't *hurt*
> > anything, but it takes up space that could be used for the
> > subject.
> > - Commit references typically use a 12-char SHA1. Again, doesn't
> > hurt anything.
> I'll fix all this in my next revision.
> Xiaowei, Gustavo,
> The issues we discussed in  should be fixed with this series. Can you help
> test this in your platforms?
OK, I will test it when I am free, and give the feedback to you.
>  ->
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