[PATCH V3 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1

Thierry Reding thierry.reding at gmail.com
Wed Jan 8 04:00:13 PST 2020


On Thu, Oct 03, 2019 at 02:50:31PM -0600, Stephen Warren wrote:
> From: Stephen Warren <swarren at nvidia.com>
> 
> For a little over a year, U-Boot has configured the flow controller to
> perform automatic RAM re-repair on off->on power transitions of the CPU
> rail1]. This is mandatory for correct operation of Tegra124. However, RAM
> re-repair relies on certain clocks, which the kernel must enable and
> leave running. PLLP is one of those clocks. This clock is shut down
> during LP1 in order to save power. Enable bypass (which I believe routes
> osc_div_clk, essentially the crystal clock, to the PLL output) so that
> this clock signal toggles even though the PLL is not active. This is
> required so that LP1 power mode (system suspend) operates correctly.
> 
> The bypass configuration must then be undone when resuming from LP1, so
> that all peripheral clocks run at the expected rate. Without this, many
> peripherals won't work correctly; for example, the UART baud rate would
> be incorrect.
> 
> NVIDIA's downstream kernel code only does this if not compiled for
> Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
> downstream code makes this change conditional upon the active CPU
> cluster. The upstream kernel currently doesn't support cluster switching,
> so this patch doesn't test the active CPU cluster ID.
> 
> [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
> 
> Reported-by: Jonathan Hunter <jonathanh at nvidia.com>
> Cc: stable at vger.kernel.org
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
> ---
> v3: No change.
> v2: No change.
> ---
>  arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
>  1 file changed, 11 insertions(+)

Patches 2-4 applied to for-5.6/arm/core, thanks.

Thierry
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