[PATCH v6 09/11] clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz

[Stephen Boyd]

Quoting Claudiu Beznea (2020-11-19 07:43:15)
> Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
> than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
> 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea at microchip.com>
> ---

Applied to clk-next