[PATCH v2 3/4] arm64: dts: cn913x: add device trees for topology B boards
kostap at marvell.com
kostap at marvell.com
Thu Dec 17 02:55:41 EST 2020
From: Konstantin Porotchkin <kostap at marvell.com>
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS files for setup "B" are based on setup "A", in which the
CP0 NAND controller enabled and CP0 SPI1 disabled.
Signed-off-by: Konstantin Porotchkin <kostap at marvell.com>
---
arch/arm64/boot/dts/marvell/Makefile | 9 +++++---
arch/arm64/boot/dts/marvell/cn9130-db-A.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/cn9130-db-B.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/{cn9130-db.dts => cn9130-db.dtsi} | 5 ++---
arch/arm64/boot/dts/marvell/cn9131-db-A.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/cn9131-db-B.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/{cn9131-db.dts => cn9131-db.dtsi} | 5 ++---
arch/arm64/boot/dts/marvell/cn9132-db-A.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/cn9132-db-B.dts | 22 ++++++++++++++++++++
arch/arm64/boot/dts/marvell/{cn9132-db.dts => cn9132-db.dtsi} | 5 ++---
10 files changed, 144 insertions(+), 12 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-B.dts
rename arch/arm64/boot/dts/marvell/{cn9130-db.dts => cn9130-db.dtsi} (99%)
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-B.dts
rename arch/arm64/boot/dts/marvell/{cn9131-db.dts => cn9131-db.dtsi} (97%)
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-A.dts
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db-B.dts
rename arch/arm64/boot/dts/marvell/{cn9132-db.dts => cn9132-db.dtsi} (97%)
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 3e5f2e7a040c..d9b924a63d89 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -13,6 +13,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
-dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
-dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
-dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-A.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-A.dts b/arch/arm64/boot/dts/marvell/cn9130-db-A.dts
new file mode 100644
index 000000000000..adb3a67a20b1
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-A.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB setup A";
+};
+
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
+ */
+
+&cp0_spi1 {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-B.dts b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
new file mode 100644
index 000000000000..57e41cacd483
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board (setup "B").
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
similarity index 99%
rename from arch/arm64/boot/dts/marvell/cn9130-db.dts
rename to arch/arm64/boot/dts/marvell/cn9130-db.dtsi
index d24294888400..8de3a552b806 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
@@ -10,8 +10,6 @@
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Marvell Armada CN9130-DB";
-
chosen {
stdout-path = "serial0:115200n8";
};
@@ -235,6 +233,7 @@
/* U54 */
&cp0_nand_controller {
+ status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&nand_pins &nand_rb>;
@@ -306,7 +305,7 @@
/* U55 */
&cp0_spi1 {
- status = "okay";
+ status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>;
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-A.dts b/arch/arm64/boot/dts/marvell/cn9131-db-A.dts
new file mode 100644
index 000000000000..a60fdee79bf8
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db-A.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9131-DB setup A";
+};
+
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
+ */
+
+&cp0_spi1 {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-B.dts b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts
new file mode 100644
index 000000000000..94e01192aed1
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board (setup "B").
+ */
+
+#include "cn9131-db-A.dts"
+
+/ {
+ model = "Marvell Armada CN9131-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/marvell/cn9131-db.dts
rename to arch/arm64/boot/dts/marvell/cn9131-db.dtsi
index 3c975f98b2a3..82471a83ad6d 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi
@@ -1,14 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2019 Marvell International Ltd.
+ * Copyright (C) 2020 Marvell International Ltd.
*
* Device tree for the CN9131-DB board.
*/
-#include "cn9130-db.dts"
+#include "cn9130-db.dtsi"
/ {
- model = "Marvell Armada CN9131-DB";
compatible = "marvell,cn9131", "marvell,cn9130",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db-A.dts b/arch/arm64/boot/dts/marvell/cn9132-db-A.dts
new file mode 100644
index 000000000000..1f2e6377afc3
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9132-db-A.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9132-DB setup A";
+};
+
+/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When SPI controller is enabled, NAND should be disabled.
+ */
+
+&cp0_spi1 {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db-B.dts b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts
new file mode 100644
index 000000000000..7137a6f22d0f
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9132-db-B.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9132-DB setup B";
+};
+
+/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
+ * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
+ * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
+ */
+
+&cp0_nand_controller {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/marvell/cn9132-db.dts
rename to arch/arm64/boot/dts/marvell/cn9132-db.dtsi
index 4ef0df3097ca..0c2d9f57318b 100644
--- a/arch/arm64/boot/dts/marvell/cn9132-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi
@@ -1,14 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2019 Marvell International Ltd.
+ * Copyright (C) 2020 Marvell International Ltd.
*
* Device tree for the CN9132-DB board.
*/
-#include "cn9131-db.dts"
+#include "cn9131-db.dtsi"
/ {
- model = "Marvell Armada CN9132-DB";
compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
"marvell,armada-ap807-quad", "marvell,armada-ap807";
--
2.17.1
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