jbrunet at baylibre.com
Fri Dec 4 09:24:09 EST 2020
On Fri 04 Dec 2020 at 10:13, Linus Walleij <linus.walleij at linaro.org> wrote:
> Hi Lisheng,
> this patch got a bit mangled but I get where you're going.
> I think Meson needs to be augmented to use hierarchical gpiolib irqchip
> because this seems to be what the system is doing.
> So start with drivers/pinctrl/meson/Kconfig and add:
> select GPIOLIB_IRQCHIP
> select IRQ_DOMAIN_HIEARARCHY
> Then use the generic hierarchical gpiolib irqchip as described
> in Documentation/driver-api/gpio/driver.rst
> git grep child_to_parent_hwirq
> for several examples of how to do this.
One reason the irqchip has not been linked to the gpio controller so far
is IRQ_EDGE_BOTH which the irqchip does not support (expect for the
latest sm1 family)
This is a problem we discussed a couple of years ago.
This HW only has 8 irqs that can each be mapped to a pin. No direct
translation can be made, we have to allocate an irq to monitor the line.
So when gpio_to_irq() was called, we had to do that allocation dynamically
to return a valid irq number. Since there was no counter part to
gpio_to_irq(), those allocation cannot be freed during the lifetime of
When drivers relying IRQ_EDGE_BOTH first try the `gpio_to_irq()`,
allocating the irq works but setting the type does not. We are then left
with unused allocated irqs (and we don't have much)
Frameworks using gpio_to_irq() are often capable() of parsing interrupt
properties directly too. So far, it was enough to work around the problem.
I admit, I have not been following gpiolib closely since then, maybe
some progress have been made
> Linus Walleij
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