[PATCH 3/4] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp
victor.liu at nxp.com
Fri Dec 4 02:33:43 EST 2020
Add support for Mixel MIPI DPHY + LVDS PHY combo IP
as found on Freescale i.MX8qxp SoC.
Cc: Guido Günther <agx at sigxcpu.org>
Cc: Kishon Vijay Abraham I <kishon at ti.com>
Cc: Vinod Koul <vkoul at kernel.org>
Cc: Rob Herring <robh+dt at kernel.org>
Cc: NXP Linux Team <linux-imx at nxp.com>
Signed-off-by: Liu Ying <victor.liu at nxp.com>
Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
index 9b23407..0afce99 100644
@@ -4,9 +4,13 @@ The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
electrical signals for DSI.
+The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
+in either MIPI-DSI PHY mode or LVDS PHY mode.
-- compatible: Must be:
+- compatible: Should be one of:
+ - "fsl,imx8qxp-mipi-dphy"
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must contain the following entries:
- "phy_ref": phandle and specifier referring to the DPHY ref clock
@@ -14,6 +18,8 @@ Required properties:
- #phy-cells: number of cells in PHY, as defined in
this must be <0>
+- fsl,syscon: Phandle to a system controller, as required by the PHY
+ in i.MX8qxp SoC.
- power-domains: phandle to power domain
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