[PATCH] ARM: davinci: mityomapl138: enable USB1 port

[Esben Haabendal]

From: Tim Iskander <iskander at criticallink.com>

Turn on the USB1 (USB 1.1) port by default for MityDSP-L138F family of
SOMs.  It is available on the SO-DIMM-200 connector.

Signed-off-by: Tim Iskander <iskander at criticallink.com>
Signed-off-by: Michael Williamson <michael.williamson at criticallink.com>
Signed-off-by: Esben Haabendal <esben at geanix.com>
---
 arch/arm/mach-davinci/board-mityomapl138.c | 31 ++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 3382b93d9a2a..489f2dc0cf33 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -554,6 +554,35 @@ static void __init mityomapl138_config_emac(void)
 		pr_warn("emac registration failed: %d\n", ret);
 }
 
+static int mityomapl138_ocic_notify(da8xx_ocic_handler_t handler)
+{
+	return 0;
+}
+
+static struct da8xx_ohci_root_hub mityomapl138_usb11_pdata = {
+	.set_power	= 0,
+	.get_power	= 0,
+	.get_oci	= 0,
+	.ocic_notify	= mityomapl138_ocic_notify,
+	.potpgt		= 0,
+};
+
+static __init void mityomapl138_usb_init(void)
+{
+	int ret;
+	u32 cfgchip2;
+
+	/* Setup the Ref. clock frequency for the MityDSP-L138 at 24 MHz. */
+	cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
+	cfgchip2 &= ~CFGCHIP2_REFFREQ;
+	cfgchip2 |=  CFGCHIP2_REFFREQ_24MHZ;
+	__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
+
+	ret = da8xx_register_usb11(&mityomapl138_usb11_pdata);
+	if (ret)
+		pr_warn("USB1 registration failed: %d\n", ret);
+}
+
 static void __init mityomapl138_init(void)
 {
 	int ret;
@@ -605,6 +634,8 @@ static void __init mityomapl138_init(void)
 	if (ret)
 		pr_warn("cpuidle registration failed: %d\n", ret);
 
+	mityomapl138_usb_init();
+
 	davinci_pm_init();
 }
 
-- 
2.28.0