[EXT] [PATCH] arm64: dts: imx8m: Add the ENET PPS interrupt

[Andy Duan]

From: Fabio Estevam <festevam at gmail.com> Sent: Wednesday, August 19, 2020 10:00 AM
> The i.MX8M SoCs have a fourth ENET interrupt dedicated to PPS (Pulse Per
> Second). Add support for it.
> 
> Suggested-by: Rogerio Nunes <rogerio.nunes at nxp.com>
> Signed-off-by: Fabio Estevam <festevam at gmail.com>

Reviewed-by: Fugang Duan <fugang.duan at nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 3 ++-
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 3 ++-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 3 ++-
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 ++-
>  4 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 76f040e4be5e..b83f400def8b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -854,7 +854,8 @@
>                                 reg = <0x30be0000 0x10000>;
>                                 interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
>                                              <GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> -                                            <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> +                                            <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 121
> + IRQ_TYPE_LEVEL_HIGH>;
>                                 clocks = <&clk
> IMX8MM_CLK_ENET1_ROOT>,
>                                          <&clk
> IMX8MM_CLK_ENET1_ROOT>,
>                                          <&clk
> IMX8MM_CLK_ENET_TIMER>, diff --git
> a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9385dd7d1a2f..746faf1cf2fb 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -741,7 +741,8 @@
>                                 reg = <0x30be0000 0x10000>;
>                                 interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
>                                              <GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> -                                            <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> +                                            <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 121
> + IRQ_TYPE_LEVEL_HIGH>;
>                                 clocks = <&clk
> IMX8MN_CLK_ENET1_ROOT>,
>                                          <&clk
> IMX8MN_CLK_ENET1_ROOT>,
>                                          <&clk
> IMX8MN_CLK_ENET_TIMER>, diff --git
> a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 9de2aa1c573c..cad2dd790bec 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -713,7 +713,8 @@
>                                 reg = <0x30be0000 0x10000>;
>                                 interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
>                                              <GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> -                                            <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> +                                            <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 121
> + IRQ_TYPE_LEVEL_HIGH>;
>                                 clocks = <&clk
> IMX8MP_CLK_ENET1_ROOT>,
>                                          <&clk
> IMX8MP_CLK_SIM_ENET_ROOT>,
>                                          <&clk
> IMX8MP_CLK_ENET_TIMER>, diff --git
> a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index f70435cf9ad5..0d02ccdb0abc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1031,7 +1031,8 @@
>                                 reg = <0x30be0000 0x10000>;
>                                 interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
>                                              <GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> -                                            <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> +                                            <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> +                                            <GIC_SPI 121
> + IRQ_TYPE_LEVEL_HIGH>;
>                                 clocks = <&clk
> IMX8MQ_CLK_ENET1_ROOT>,
>                                          <&clk
> IMX8MQ_CLK_ENET1_ROOT>,
>                                          <&clk
> IMX8MQ_CLK_ENET_TIMER>,
> --
> 2.17.1