[PATCH] arm64: cpu_errata: Remove ARM64_MISMATCHED_CACHE_LINE_SIZE

Suzuki K Poulose suzuki.poulose at arm.com
Wed Sep 19 03:53:43 PDT 2018

On 09/19/2018 11:41 AM, Will Deacon wrote:
> There's no need to treat mismatched cache-line sizes reported by CTR_EL0
> differently to any other mismatched fields that we treat as "STRICT" in
> the cpufeature code. In both cases we need to trap and emulate EL0
> accesses to the register, so drop ARM64_MISMATCHED_CACHE_LINE_SIZE and
> rely on ARM64_MISMATCHED_CACHE_TYPE instead.

The only reason was to avoid trapping the kernel accesses of CTR_EL0
for cache line sizes if there were no differences. If we are ok with
that, I am fine with the patch.


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