[PATCH v2 1/2] coresight: tmc: Fix byte-address alignment for RRP

Mathieu Poirier mathieu.poirier at linaro.org
Tue Sep 11 12:54:51 PDT 2018


On Tue, Sep 11, 2018 at 03:52:45PM +0800, Leo Yan wrote:
> From the comment in the code, it claims the requirement for byte-address
> alignment for RRP register: 'for 32-bit, 64-bit and 128-bit wide trace
> memory, the four LSBs must be 0s. For 256-bit wide trace memory, the
> five LSBs must be 0s'.  This isn't consistent with the program, the
> program sets five LSBs as zeros for 32/64/128-bit wide trace memory and
> set six LSBs zeros for 256-bit wide trace memory.
> 
> After checking with the CoreSight Trace Memory Controller technical
> reference manual (ARM DDI 0461B, section 3.3.4 RAM Read Pointer
> Register), it proves the comment is right and the program does wrong
> setting.
> 
> This patch fixes byte-address alignment for RRP by following correct
> definition in the technical reference manual.
> 
> Cc: Mathieu Poirier <mathieu.poirier at linaro.org>
> Cc: Mike Leach <mike.leach at linaro.org>
> Signed-off-by: Leo Yan <leo.yan at linaro.org>
> ---
>  drivers/hwtracing/coresight/coresight-tmc-etf.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index 4bf3bfd..b54a3db 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -417,10 +417,10 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
>  		case TMC_MEM_INTF_WIDTH_32BITS:
>  		case TMC_MEM_INTF_WIDTH_64BITS:
>  		case TMC_MEM_INTF_WIDTH_128BITS:
> -			mask = GENMASK(31, 5);
> +			mask = GENMASK(31, 4);
>  			break;
>  		case TMC_MEM_INTF_WIDTH_256BITS:
> -			mask = GENMASK(31, 6);
> +			mask = GENMASK(31, 5);
>  			break;
>  		}
>  
> -- 
> 2.7.4
>

Applied.

Thanks,
Mathieu 



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