SoCFPGA Arria10 timer hang
dinh.nguyen at intel.com
Fri Sep 7 14:40:44 PDT 2018
> -----Original Message-----
> From: Marek Vasut <marex at denx.de>
> Sent: Friday, September 7, 2018 2:46 PM
> To: linux ARM <linux-arm-kernel at lists.infradead.org>
> Cc: Nguyen, Dinh <dinh.nguyen at intel.com>; See, Chin Liang
> <chin.liang.see at intel.com>; Tan, Ley Foon <ley.foon.tan at intel.com>
> Subject: SoCFPGA Arria10 timer hang
> Latest upstream U-Boot (2018.09-rc3 and newer) properly handles reset on the
> SoCFPGA Arria10. Since it uses only SP Timer 2, the remaining timers (0, 1, 3) are
> left in reset state.
> Linux, on the other hand, picks the last timer in DT, which is SP Timer 3, as a
> system timer. But since on Arria10 it doesn't unreset the timer and depends on
> bootloader behavior, Linux just hangs very early on there.
> The Arria10 DTSI lacks any SP Timer "reset" phandles, so the reset controller
> cannot unreset those timers. Adding those reset phandles is the first step to fix
> this problem.
> Next one is drivers/clocksource/dw_apb_timer_of.c, which lacks support for
> reset control at all. Adding reset controller support there is another step.
> But there is a problem, the reset controller driver comes up much later than the
> timer. This is something I didn't have time to solve. If any of you can continue
> fixing this, that'd be nice. I can share the patches I have thus far too.
I can look into it. Are your patches going down the line of having a version of the
SoCFPGA reset driver that gets registered early and uses the simple reset driver?
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