[PATCH] clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration
Stephen Boyd
sboyd at kernel.org
Tue May 15 15:34:48 PDT 2018
Quoting Sekhar Nori (2018-05-07 04:34:57)
> USB0 48MHz PHY clock registration fails on DA830 because the
> da8xx-cfgchip clock driver cannot get a reference to USB0
> LPSC clock.
>
> The USB0 LPSC needs to be enabled during PHY clock enable. Setup
> the clock lookup correctly to fix this.
>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>
> ---
Applied to clk-next
Did this need a fixes tag? And should it go into 4.17 final? Or it's not
causing problems right now?
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