[PATCH v6 0/4] Fix issues with huge mapping in ioremap for ARM64
Chintan Pandya
cpandya at codeaurora.org
Wed Mar 28 05:10:26 PDT 2018
I goofed up in making a patch file so enumeration is wrong.
I'll upload v7
On 3/28/2018 4:28 PM, Chintan Pandya wrote:
> This series of patches are follow up work (and depends on)
> Toshi Kani <toshi.kani at hpe.com>'s patches "fix memory leak/
> panic in ioremap huge pages".
>
> This series of patches are tested on 4.9 kernel with Cortex-A75
> based SoC.
>
> These patches can also go into '-stable' branch (if accepted)
> for 4.6 onwards.
>
> From V5->V6:
> - Use __flush_tlb_kernel_pgtable() for both PUD and PMD. Remove
> "bool tlb_inv" based variance as it is not need now
> - Re-naming for consistency
>
> From V4->V5:
> - Add new API __flush_tlb_kernel_pgtable(unsigned long addr)
> for kernel addresses
>
> From V3->V4:
> - Add header for 'addr' in x86 implementation
> - Re-order pmd/pud clear and table free
> - Avoid redundant TLB invalidatation in one perticular case
>
> From V2->V3:
> - Use the exisiting page table free interface to do arm64
> specific things
>
> From V1->V2:
> - Rebased my patches on top of "[PATCH v2 1/2] mm/vmalloc:
> Add interfaces to free unmapped page table"
> - Honored BBM for ARM64
>
> Chintan Pandya (4):
> ioremap: Update pgtable free interfaces with addr
> arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable
> arm64: Implement page table free interfaces
> Revert "arm64: Enforce BBM for huge IO/VMAP mappings"
>
> arch/arm64/include/asm/tlbflush.h | 6 ++++++
> arch/arm64/mm/mmu.c | 37 +++++++++++++++++++++++++------------
> arch/x86/mm/pgtable.c | 6 ++++--
> include/asm-generic/pgtable.h | 8 ++++----
> lib/ioremap.c | 4 ++--
> 5 files changed, 41 insertions(+), 20 deletions(-)
>
Chintan
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