[PATCH v2 5/5] clk: mediatek: update clock driver of MT2712

[Stephen Boyd]

Quoting Weiyi Lu (2018-03-12 00:03:42)
> According to ECO design change,
> 1. add new clock mux data and change some
> 2. add new clock gate data and clock factor data
> 3. change status register offset of infra subsystem
> 
> Signed-off-by: Weiyi Lu <weiyi.lu at mediatek.com>
> ---

Applied to clk-next