[PATCH 2/2] clk: mediatek: fix PWM clock source by adding a fixed-factor clock
Stephen Boyd
sboyd at kernel.org
Mon Mar 19 13:25:39 PDT 2018
Quoting sean.wang at mediatek.com (2018-02-28 19:27:51)
> From: Sean Wang <sean.wang at mediatek.com>
>
> The clock for which all PWM devices on MT7623 or MT2701 actually depending
> on has to be divided by four from its parent clock axi_sel in the clock
> path prior to PWM devices.
>
> Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
> clock axi_sel allows that PWM devices can have the correct resolution
> calculation.
>
> Cc: stable at vger.kernel.org
> Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
> Signed-off-by: Sean Wang <sean.wang at mediatek.com>
> ---
Applied to clk-next
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