[PATCH] perf vendor events arm64: Enable JSON events for ThunderX2 B0

[John Garry]

On 15/03/2018 15:53, William Cohen wrote:
> On 03/07/2018 11:14 PM, Ganapatrao Kulkarni wrote:
>> On Thu, Mar 8, 2018 at 12:01 AM, William Cohen <wcohen at redhat.com> wrote:
>>> On 03/07/2018 12:35 PM, Ganapatrao Kulkarni wrote:
>>>> Hi Will Cohen,
>>>>
>>>> On Wed, Mar 7, 2018 at 8:08 PM, Arnaldo Carvalho de Melo
>>>> <acme at kernel.org> wrote:
>>>>> Em Wed, Mar 07, 2018 at 09:32:05AM -0500, William Cohen escreveu:
>>>>>> On 03/07/2018 06:08 AM, Ganapatrao Kulkarni wrote:
>>>>>>> There is MIDR change on ThunderX2 B0, adding an entry to mapfile
>>>>>>> to enable JSON events for B0.
>>>>>>>
>>>>>>> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni at cavium.com>
>>>>>
>>>>> Ganapatrao, can you please take this in consideration and if agreeing
>>>>> send a v2 patch?
>>>>>
>>>>> With that I can add an Acked-by: wcohen, Right?
>>>>>
>>>>> - Arnaldo
>>>>>>> ---
>>>>>>>  tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>>>>>>>  1 file changed, 1 insertion(+)
>>>>>>>
>>>>>>> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>>>>>> index e61c9ca..93c5d14 100644
>>>>>>> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>>>>>> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
>>>>>>> @@ -13,4 +13,5 @@
>>>>>>>  #
>>>>>>>  #Family-model,Version,Filename,EventType
>>>>>>>  0x00000000420f5160,v1,cavium,core
>>>>>>> +0x00000000430f0af0,v1,cavium,core
>>>>>>>  0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
>>>>>>>
>>>>>>
>>>>>> Hi,
>>>>>> Like the cortex-a53 the last digit '0' of the match for the MIDR should be replaced with [[:xdigit:]] to allow for possible future revisions of chip:
>>>>
>>>> for arm64 implementation,  bits 3:0(Revision) and bits 23:20(Variant)
>>>> are ignored/dont-care.
>>>
>>> Thanks for pointing that out.  See the code masking out those bits in linux/toos/perf/arch/util/header.c. For the ppc64 it just copies the equivalent of the MIDR including the revision bits. Thus, the need for regular expression matching to avoid having to create a new entry for each revision.
>>
>> It is same for arm64 too, there is no need to add an entry for every
>> revision change,  need to add when part number changes.
>> This patch is not intended to add entry for revision change, the fact
>> of the matter is that, there  is complete MIDR change (vulcan to
>> thunderx2) in B0.
>> as per current arm64
>> implementation(.tools/perf/arch/arm64/util/header.c), it is not
>> required to have any dontcare marking in mapfile for revision/variant
>> bits.
>>
>> thanks
>> Ganapat
>
> Hi Ganapat,
>
> Would it make more sense to pass the MIDR value unmodified and then use regular expressions in mapfile.csv to match the values?  If an event on a particular processor revision is broken or unusable it can be excluded from the list of events with a corrected list of events.  There certainly have been errata listing events that do not work on specific revisions of armv8 processor implementations.
>

Then there are vendors who do not always properly implemenent MIDR or 
IIDRs (people who live in glass houses...).

Btw, topic originally discussed here:
https://lkml.org/lkml/2017/5/2/113

Thanks,
John

> -Will
>
>
> .
>