[PATCH v6 09/41] dt-bindings: clock: New bindings for TI Davinci PSC

[Rob Herring]

On Sat, Jan 20, 2018 at 11:13:48AM -0600, David Lechner wrote:
> This adds a new binding for the Power Sleep Controller (PSC) for the
> mach-davinci family of processors.
> 
> Note: Although TI Keystone has a very similar PSC, we are not using the
> existing bindings. Keystone is using a legacy one-node-per-clock binding
> (actually two nodes if you count the separate reset binding for the same
> IP block). Also, some davinci LPSCs have quirks that aren't handled by
> the keystone bindings, so we would be adding one compatible string per
> clock with quirks instead of just a new compatible string for each
> controller.
> 
> Signed-off-by: David Lechner <david at lechnology.com>
> ---
> 
> v6 changes:
> - added clocks and clock-names properties
> - expanded examples
> 
>  .../devicetree/bindings/clock/ti/davinci/psc.txt   | 66 ++++++++++++++++++++++
>  1 file changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
> new file mode 100644
> index 0000000..0c2d2bd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
> @@ -0,0 +1,66 @@
> +Binding for TI DaVinci Power Sleep Controller (PSC)
> +
> +The PSC provides power management, clock gating and reset functionality. It is
> +primarily used for clocking.
> +
> +Required properties:
> +- compatible: shall be one of:
> +	- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
> +	- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
> +- reg: physical base address and size of the controller's register area
> +- #clock-cells: from common clock binding; shall be set to 1
> +- clocks: phandles to clocks corresponding to the clock-names property
> +- clock-names: list of parent clock names - depends on compatible value
> +	- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
> +	  "pll0_sysclk4", "pll0_sysclk6", "async1"
> +	- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
> +
> +Optional properties:
> +- #reset-cells: from reset binding; shall be set to 1 - only applicable when
> +  at least one local domain provides a local reset.
> +
> +Consumers:
> +
> +	Clock and reset consumers shall use the local power domain module ID
> +	(LPSC) as the index corresponding to the clock cell. Refer to the
> +	device-specific	datasheet to find these numbers. NB: Most local domains
> +	only provide a clock and not a reset.
> +
> +Examples:
> +
> +	psc0: clock-controller at 10000 {
> +		compatible = "ti,da850-psc0";
> +		reg = <0x10000 0x1000>;
> +		#clock-cells = <1>;
> +		#reset-cells = <1>;
> +		clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
> +			 <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
> +		clock_names = "pll0_sysclk1", "pll0_sysclk2",

Should be clock-names

> +			      "pll0_sysclk4", "pll0_sysclk6", "async1";
> +	};
> +	psc1: clock-controller at 227000 {
> +		compatible = "ti,da850-psc1";
> +		reg = <0x227000 0x1000>;
> +		#clock-cells = <1>;
> +		clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
> +		clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";

ditto

With that,

Reviewed-by: Rob Herring <robh at kernel.org>