[PATCH v1] EDAC, armv8: Add Cache Error Reporting driver for ARMv8 processors

[Mark Rutland]

On Mon, Jan 15, 2018 at 05:00:08PM -0800, Kyle Yan wrote:
> On 2018-01-15 06:44, Mark Rutland wrote:
> > On Fri, Jan 12, 2018 at 04:50:26PM -0800, Kyle Yan wrote:
> > > +	if (!IS_ENABLED(CONFIG_EDAC_ARMV8_POLL)) {
> > > +		fail += request_erp_irq(pdev, "l1-l2-irq",
> > > +				"l1_l2_irq",
> > > +				armv8_l1_l2_handler, drv, 1);
> > > +
> > > +		fail += request_erp_irq(pdev, "l3-scu-irq",
> > > +				"l3_scu_irq",
> > > +				armv8_l3_scu_handler, drv, 0);
> > 
> > SCU isn't an architectural concept, and a combined l1-l2 interrupt
> > sounds very specific to a particular implementation.
> > 
> Can do a rename to something more akin to "private_cache_irq" and
> "shared_cache_irq".

My concern is more that whatever interrupts exist (and how they are
combined etc) is going to be specific to a given platform. Regardless of
the names we choose, the semantic of that name is platform-dependent.

I think to support interrupts, we need an explicit description of the
error node topology, with the interrupts associated with that topology
somehow. Names alone are not sufficient.

Thanks,
Mark.