[PATCH v6 06/13] arm64: kernel: Prepare for a DISR user
Suzuki K Poulose
Suzuki.Poulose at arm.com
Tue Jan 16 03:11:17 PST 2018
On 15/01/18 19:38, James Morse wrote:
> KVM would like to consume any pending SError (or RAS error) after guest
> exit. Today it has to unmask SError and use dsb+isb to synchronise the
> CPU. With the RAS extensions we can use ESB to synchronise any pending
> SError.
>
> Add the necessary macros to allow DISR to be read and converted to an
> ESR.
>
> We clear the DISR register when we enable the RAS cpufeature, and the
> kernel has not executed any ESB instructions. Any value we find in DISR
> must have belonged to firmware. Executing an ESB instruction is the
> only way to update DISR, so we can expect firmware to have handled
> any deferred SError. By the same logic we clear DISR in the idle path.
>
> Signed-off-by: James Morse <james.morse at arm.com>
> Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
James,
Looks fine to me. minor nit below
> #endif /* __ASM_EXCEPTION_H */
> diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
> index 023cacb946c3..cee4ae25a5d1 100644
> --- a/arch/arm64/include/asm/processor.h
> +++ b/arch/arm64/include/asm/processor.h
> @@ -216,6 +216,7 @@ static inline void spin_lock_prefetch(const void *ptr)
>
> int cpu_enable_pan(void *__unused);
> int cpu_enable_cache_maint_trap(void *__unused);
> +int cpu_clear_disr(void *__unused);
>
> /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
> #define SVE_SET_VL(arg) sve_set_current_vl(arg)
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 1281bc8263c2..115b89aeec00 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -279,6 +279,7 @@
> #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
>
> #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
> +#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
minor nit: additional white space ^^^
With that fixed,
Reviewed-by: Suzuki K Poulose <suzuki.poulose at arm.com>
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