[PATCH v6 05/13] arm64: Unconditionally enable IESB on exception entry/return for firmware-first

[Marc Zyngier]

On 15/01/18 19:38, James Morse wrote:
> ARM v8.2 has a feature to add implicit error synchronization barriers
> whenever the CPU enters or returns from an exception level. Add this to the
> features we always enable. CPUs that don't support this feature will treat
> the bit as RES0.
> 
> This feature causes RAS errors that are not yet visible to software to
> become pending SErrors. We expect to have firmware-first RAS support
> so synchronised RAS errors will be take immediately to EL3.
> Any system without firmware-first handling of errors will take the SError
> either immediatly after exception return, or when we unmask SError after
> entry.S's work.
> 
> Adding IESB to the ELx flags causes it to be enabled by KVM and kexec
> too.
> 
> Platform level RAS support may require additional firmware support.
> 
> Cc: Christoffer Dall <christoffer.dall at linaro.org>
> Cc: Marc Zyngier <marc.zyngier at arm.com>
> Suggested-by: Will Deacon <will.deacon at arm.com>
> Link: https://www.spinics.net/lists/kvm-arm/msg28192.html
> Signed-off-by: James Morse <james.morse at arm.com>

Acked-by: Marc Zyngier <marc.zyngier at arm.com>

	M.
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