EDAC driver for ARMv8 L1/L2 cache

[York Sun]

On 01/15/2018 03:23 PM, Borislav Petkov wrote:
> On Mon, Jan 15, 2018 at 04:19:09PM +0000, York Sun wrote:
>> I have different plan on the driver. Since I don't get interrupt on
>> correctable errors,
> 
> Is that something nxp-specific or generic ARM64 thing?
> 
> If it is the former, then you'd need a special driver for your hardware,
> as much as I don't like the idea of having per-vendor driver...
> 
It is generic ARM64 thing. I believe only SError interrupt is available.
But SError can be caused by many reasons. For L1/L2 only uncorrectable
errors trigger SError. My first step is to deal with correctable errors
and to raise a flag somehow (Haven't think that through yet) when
excessive errors are reported. Next step I will deal with the
uncorrectable errors with interrupt.

York