EDAC driver for ARMv8 L1/L2 cache

[Mark Rutland]

On Fri, Jan 12, 2018 at 06:12:51PM +0100, Borislav Petkov wrote:
> On Fri, Jan 12, 2018 at 04:48:05PM +0000, York Sun wrote:
> > I see Stratix10 has A53 core. I am concerned on reading the
> > CPUMERRSR_EL1 and L2MERRSR_EL1. The are IMPLEMENTATION DEFINED
> > registers. They may not be available on all SoCs, or all time.
> 
> Is there something like CPUID on x86, on ARM64 which denotes presence of
> a certain feature?
> 
> Or is that thing devicetree?

We have ID registers, like CPUID, but for various reasons those aren't
sufficient to guarantee that IMPLEMENTATION DEFINED features can be
used.

If we want to support this, we'd certainly need something in DT.

For ACPI systems I'd expect this to be hidden behind APEI or similar,
with the kernel staying well clear of these registers.

Thanks,
Mark.