EDAC driver for ARMv8 L1/L2 cache

[Borislav Petkov]

On Fri, Jan 12, 2018 at 04:48:05PM +0000, York Sun wrote:
> I see Stratix10 has A53 core. I am concerned on reading the
> CPUMERRSR_EL1 and L2MERRSR_EL1. The are IMPLEMENTATION DEFINED
> registers. They may not be available on all SoCs, or all time.

Is there something like CPUID on x86, on ARM64 which denotes presence of
a certain feature?

Or is that thing devicetree?

-- 
Regards/Gruss,
    Boris.

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