[PATCH v7 3/5] clk: aspeed: Add platform driver and register PLLs

[Stephen Boyd]

On 12/22, Joel Stanley wrote:
> This registers a platform driver to set up all of the non-core clocks.
> 
> The clocks that have configurable rates are now registered.
> 
> Reviewed-by: Andrew Jeffery <andrew at aj.id.au>
> Signed-off-by: Joel Stanley <joel at jms.id.au>
> --
> v6:
>  - Add Andrew's reviewed-by
> v5:
>  - Remove eclk configuration. We do not have enough information to
>  correctly implement the mux and divisor, so it will have to be
>  implemented in the future
> v4:
>  - Add eclk div table to fix ast2500 calculation
>  - Add defines to document the BIT() macros
>  - Pass dev where we can when registering clocks
>  - Check for errors when registering clk_hws
> v3:
>  - Fix bclk and eclk calculation
>  - Separate out ast2400 and ast25000 for pll calculation
> ---

Applied to clk-next

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