[PATCH 2/2] drm/sun4i: Handle DRM_MODE_FLAG_**SYNC_POSITIVE correctly
maxime.ripard at bootlin.com
Fri Feb 16 07:50:49 PST 2018
On Thu, Feb 15, 2018 at 07:05:56PM +0100, Giulio Benetti wrote:
> > If so, and if remember the captures properly, the sampling would occur
> > right before the rise, and not really around the fall.
> > Would 2/3 be better here?
> Yes, you're right, 2/3 phase is better:
> 1/3 phase: https://pasteboard.co/H4VehON.png
> 2/3 phase: https://pasteboard.co/H4Veq8a.png
> Take a look at the bit in middle(yellow) sampled by clock(blue).
> Rising edge is almost in the middle of D0 bit.
> > > According to scope captures above on both A20 and A33.
> > > Unfortunately I don't have other boards for the other SoCs to take captures.
> > >
> > > What do you think?
> > I guess we can make that part applicable to all SoCs, we haven't seen
> > any significant differences on those part.
> So let's keep:
> - As normal(rising edge) => IO_POL_REG "0x2 => 2/3 phase"
> - As inverted(falling edge) => IO_POL_REG "0x0 => normal phase"
I was actually thinking 1/3 for rising, 2/3 for falling.
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
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