[PATCH 4/6] ARM: dts: aspeed: Add LPC clock phandles
Joel Stanley
joel at jms.id.au
Sun Feb 11 23:43:23 PST 2018
The LPC device uses LCLK.
Tested-by: Lei YU <mine260309 at gmail.com>
Reviewed-by: Andrew Jeffery <andrew at aj.id.au>
Signed-off-by: Joel Stanley <joel at jms.id.au>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 1 +
arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 8b18176dca59..48c28a71ae7e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -233,6 +233,7 @@
lpc_ctrl: lpc-ctrl at 0 {
compatible = "aspeed,ast2400-lpc-ctrl";
reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index e0b6803f6845..8eac57c33880 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -283,6 +283,7 @@
lpc_ctrl: lpc-ctrl at 0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
--
2.15.1
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