EDAC driver for ARMv8 L1/L2 cache

[York Sun]

On 01/15/2018 03:52 PM, Borislav Petkov wrote:
> On Mon, Jan 15, 2018 at 11:28:14PM +0000, York Sun wrote:
>> It is generic ARM64 thing. I believe only SError interrupt is available.
> 
> So if it is, then I'd suggest you hammer out a proper design with the
> ARM folks.
> 

I made some progress and need some help on coding. On the platform I am
working on, it has A53 cores. Each A53 core has a signal nINTERRIRQ.
They are connected to one GIC interrupt. I managed to inject errors to
some safe address without triggering system error and I got the
interrupt. I will need to find out which core has errors by reading
register on each core (and clear the interrupt). How can I do this
within interrupt service routine? I tried to use
smp_call_function_single() but it doesn't like the IRQ being disabled.

Any suggestion is appreciated!

York