[PATCH] clk: mediatek: correct the clocks for MT2701 HDMI PHY module

[Ryder Lee]

On Mon, 2018-04-16 at 09:34 -0700, Stephen Boyd wrote:
> Quoting Ryder Lee (2018-04-15 19:31:58)
> > The hdmitx_dig_cts clock signal is not a child of clk26m,
> > and the actual output of the PLL block is derived from
> > the tvdpll via a configurable PLL post-divider.
> > 
> > It is used as the PLL reference input to the HDMI PHY module.
> > 
> > Signed-off-by: Chunhui Dai <chunhui.dai at mediatek.com>
> > Signed-off-by: Ryder Lee <ryder.lee at mediatek.com>
> 
> Any sort of Fixes: tag here?
> 

Yes, I've already sent a new one.

Thanks