[PATCH 0/6] Support PPTT for ARM64

[Jeremy Linton]

On 09/14/2017 01:49 PM, Jeremy Linton wrote:
> ACPI 6.2 adds the Processor Properties Topology Table (PPTT), which is
> used to describe the processor and cache topologies. Ideally it is
> used to extend/override information provided by the hardware, but
> right now ARM64 is entirely dependent on firmware provided tables.

Hi,

So there is a problem with this patch set when cache nodes are 
referenced by cpu nodes with the intention that the resulting caches 
aren't shared, even though the PPTT cache node is shared. The code uses 
the node reference when determining if caches are shared. This means 
that it makes a mistake and thinks that all the (say L1) caches are 
shared because they share a PPTT cache node.

Its a fairly small tweak, I will re-post this set.




> 
> This patch parses the table for the cache topology and CPU topology.
> For the latter we also add an additional topology_cod_id() macro,
> and a package_id for arm64. Initially the physical id will match
> the cluster id, but we update users of the cluster to utilize
> the new macro. When we enable PPTT for the arm64 the cluster/socket
> starts to differ. Because of this we also make some dynamic decisions
> about mapping thread/core/cod/socket to the thread/socket used by the
> scheduler.
> 
> For example on juno:
> 
> [root at mammon-juno-rh topology]# lstopo-no-graphics
> Machine (7048MB)
>    Package L#0
>      L2 L#0 (1024KB) + Core L#0
>        L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
>        L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)
>        L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2)
>        L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3)
>      L2 L#1 (2048KB) + Core L#1
>        L1d L#4 (32KB) + L1i L#4 (48KB) + PU L#4 (P#4)
>        L1d L#5 (32KB) + L1i L#5 (48KB) + PU L#5 (P#5)
>    HostBridge L#0
>      PCIBridge
>        PCIBridge
>          PCIBridge
>            PCI 1095:3132
>              Block(Disk) L#0 "sda"
>          PCIBridge
>            PCI 1002:68f9
>              GPU L#1 "renderD128"
>              GPU L#2 "card0"
>              GPU L#3 "controlD64"
>          PCIBridge
>            PCI 11ab:4380
>              Net L#4 "enp8s0"
> 
> 
> Jeremy Linton (6):
>    ACPI/PPTT: Add Processor Properties Topology Table parsing
>    ACPI: Enable PPTT support on ARM64
>    drivers: base: cacheinfo: arm64: Add support for ACPI based firmware
>      tables
>    Topology: Add cluster on die macros and arm64 decoding
>    arm64: Fixup users of topology_physical_package_id
>    arm64: topology: Enable ACPI/PPTT based CPU topology.
> 
>   arch/arm64/Kconfig                |   1 +
>   arch/arm64/include/asm/topology.h |   4 +-
>   arch/arm64/kernel/cacheinfo.c     |  23 +-
>   arch/arm64/kernel/topology.c      |  76 +++++-
>   drivers/acpi/Makefile             |   1 +
>   drivers/acpi/arm64/Kconfig        |   3 +
>   drivers/acpi/pptt.c               | 508 ++++++++++++++++++++++++++++++++++++++
>   drivers/base/cacheinfo.c          |  17 +-
>   drivers/clk/clk-mb86s7x.c         |   2 +-
>   drivers/cpufreq/arm_big_little.c  |   2 +-
>   drivers/firmware/psci_checker.c   |   2 +-
>   include/linux/cacheinfo.h         |  10 +-
>   include/linux/topology.h          |   5 +
>   13 files changed, 634 insertions(+), 20 deletions(-)
>   create mode 100644 drivers/acpi/pptt.c
>