[PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register.
michal.simek at xilinx.com
Fri Sep 15 00:49:41 PDT 2017
On 14.9.2017 16:34, Andrew Lunn wrote:
> On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:
>> To clear Speed Selection in MDIO control register(0x10),
>> ie, clear bits 6 and 13 to zero while keeping other bits same.
>> Before AND operation,The Mask value has to be perform with bitwise NOT
>> operation (ie, ~ operator)
>> This patch clears current speed selection before writing the
>> new speed settings to gmii2rgmii converter
> Hi Fahad
> I expect you will find other issues with this driver. I pointed some
> out at the time it is submitted, but the developers went quiet as soon
> as it was accepted.
Can you please point me to that email?
I will create ticket about it in our system to get them resolved.
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