[PATCH v5 3/7] clk: at91: add audio pll clock drivers

Stephen Boyd sboyd at codeaurora.org
Fri Sep 1 15:55:14 PDT 2017

On 08/10, Quentin Schulz wrote:
> This new clock driver set allows to have a fractional divided clock that
> would generate a precise clock particularly suitable for audio
> applications.
> The main audio pll clock has two children clocks: one that is connected
> to the PMC, the other that can directly drive a pad. As these two routes
> have different enable bits and different dividers and divider formulas,
> they are handled by two different drivers. Each of them could modify the
> rate of the main audio pll parent.
> The main audio pll clock can output 620MHz to 700MHz.
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> Signed-off-by: Quentin Schulz <quentin.schulz at free-electrons.com>
> Acked-by: Boris Brezillon <boris.brezillon at free-electrons.com>
> ---

Applied to clk-next

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