[PATCH 11/11] ARM: dts: Add PCLK to the Aspeed watchdogs

[Linus Walleij]

On Wed, Oct 11, 2017 at 5:48 AM, Andrew Jeffery <andrew at aj.id.au> wrote:
> On Sat, 2017-08-12 at 20:43 +0200, Linus Walleij wrote:
>> This adds the PCLK clock to the Aspeed watchdog blocks.
>> I am not directly familiar with the Aspeed clocking, but
>> since the IP is derived from Faraday FTWDT010 it probably
>> has the ability to run the watchdog on the PCLK if
>> desired
>
> This is true for the AST2400, but not the AST2500 where the only option
> is EXTCLK (1MHz).

The IP block/cell certainly has a PCLK even if it cannot be used
to drive the watchdog timer. It is necessary to interface the
SoC interconnect.

>> > +                           clocks = <&clk_apb>;
>> +                             clock-names = "PCLK";
>
> Given the comment above, shouldn't we be doing something like the
> following instead for each of the watchdogs?
>
> +                               faraday,use-extclk;
> +                               clock-names = "EXTCLK";

So that will be added too, later, when there is a 1MHz clock
to reference in the device tree. I guess after Joel's patches.

Yours,
Linus Walleij