[PATCH] clk: imx: clk-imx6ul: allow lcdif_pre_sel to change parent rate

[Stephen Boyd]

On 10/12, Philipp Zabel wrote:
> Allowing the lcdif_pre_sel to propagate rate changes to its parent PLL
> allows more fine grained control over the LCDIF pixel clock rate.
> 
> For example, the Innovision AT043TN24 LCD panel described in the
> imx6ul-14x14-evk device tree requires a 9 MHz pixel clock.
> Before this patch, the lcdif_pre_sel clock rate is fixed, and just
> setting the lcdif_pred and lcdif_podf dividers only allows to get as
> close as about 8.44 MHz:
> 
>     pll3                                  1            1   480000000 0 0
>        pll3_bypass                        1            1   480000000 0 0
> 	  pll3_usb_otg                    1            1   480000000 0 0
> 	     pll3_pfd1_540m               1            1   540000000 0 0
> 		lcdif_pre_sel             1            1   540000000 0 0
> 		   lcdif_pred             1            1    67500000 0 0
> 		      lcdif_podf           1            1     8437500 0 0
> 			 lcdif_pix           1            1     8437500 0 0
> 
> Once lcdif_pre_sel is allowed to propagate rate requests to its parent,
> the actual pixel clock matches the requested value:
> 
>     pll3                                  1            1   480000000 0 0
>        pll3_bypass                        1            1   480000000 0 0
> 	  pll3_usb_otg                    1            1   480000000 0 0
> 	     pll3_pfd1_540m               1            1   288000000 0 0
> 		lcdif_pre_sel             1            1   288000000 0 0
> 		   lcdif_pred             1            1    36000000 0 0
> 		      lcdif_podf           1            1     9000000 0 0
>                          lcdif_pix           1            1     9000000 0 0
> 
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
> ---

Applied to clk-next

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