PROBLEM: ARM Cache policy on single armv7 processor lead to low DRAM performance

[Pavel Machek]

Hi!

> We met some DDR performance issue caused by armv7 cache policy, hope
> you can help.
> On a single armv7(Cortex-A7) processor system, the arm linux kernel,
> without CONFIG_SMP, the cache policy is set to write-back no-allocate,
> which lead to very low DRAM speed,
> around 7MB/s for write, 28MB/s for read.
> If enable CONFIG_SMP and CONFIG_SMP_ON_UP, then the cache policy is
> changed to write-back read-write-allocate, and the DRAM speed is
> improved a lot, around 120MB/s for write, 160MB/s for read.

Just out of curiosity, is not that still 10x lower than expected? What kind of
system is that?
									Pavel

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