[PATCH V2 3/5] pinctrl: imx: add soc specific mux_mode mask and shift property

[Shawn Guo]

On Fri, May 19, 2017 at 03:05:43PM +0800, Dong Aisheng wrote:
> MX7ULP MUX mode mask and shift bit is different from VF610.
> Let's make it a platform specific property for the later easy of
> adding MX7ULP support.
> 
> One trick in exist code that Vybrid hardcoded the config part
> as 0xffff because its mux_config register BIT[15-0] are all configs
> part. But it's not true in ULP, so use mux_mask instead to address
> the difference.
> 
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Shawn Guo <shawnguo at kernel.org>
> Cc: Stefan Agner <stefan at agner.ch>
> Cc: Bai Ping <ping.bai at nxp.com>
> Signed-off-by: Fugang Duan <fugang.duan at nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong at nxp.com>

Acked-by: Shawn Guo <shawnguo at kernel.org>