[PATCH 4/6] tty: serial: lpuart: add imx7ulp support

[Dong Aisheng]

On Wed, May 10, 2017 at 01:37:07PM -0700, Stefan Agner wrote:
> On 2017-05-09 23:14, Dong Aisheng wrote:
> > Hi Stefan,
> > 
> > On Wed, May 10, 2017 at 12:10 PM, Stefan Agner <stefan at agner.ch> wrote:
> >> On 2017-05-09 00:50, Dong Aisheng wrote:
> >>> The lpuart of imx7ulp is basically the same as ls1021a. It's also
> >>> 32 bit width register, but unlike ls1021a, it's little endian.
> >>> Besides that, imx7ulp lpuart has a minor different register layout
> >>> from ls1021a that it has four extra registers (verid, param, global,
> >>> pincfg) located at the beginning of register map, which are currently
> >>> not used by the driver and less to be used later.
> >>>
> >>> To ease the register difference handling, we add a reg_off member
> >>> in lpuart_soc_data structure to represent if the normal
> >>> lpuart32_{read|write} requires plus a offset to hide the issue.
> >>>
> >>> Cc: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
> >>> Cc: Jiri Slaby <jslaby at suse.com>
> >>> Cc: Fugang Duan <fugang.duan at nxp.com>
> >>> Cc: Stefan Agner <stefan at agner.ch>
> >>> Cc: Mingkai Hu <Mingkai.Hu at nxp.com>
> >>> Cc: Yangbo Lu <yangbo.lu at nxp.com>
> >>> Signed-off-by: Dong Aisheng <aisheng.dong at nxp.com>
> >>> ---
> >>>  drivers/tty/serial/fsl_lpuart.c | 21 ++++++++++++++++++---
> >>>  1 file changed, 18 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
> >>> index bddd041..1cdb3f9 100644
> >>> --- a/drivers/tty/serial/fsl_lpuart.c
> >>> +++ b/drivers/tty/serial/fsl_lpuart.c
> >>> @@ -231,7 +231,11 @@
> >>>  #define DEV_NAME     "ttyLP"
> >>>  #define UART_NR              6
> >>>
> >>> +/* IMX lpuart has four extra unused regs located at the beginning */
> >>> +#define IMX_REG_OFF  0x10
> >>> +
> >>>  static bool lpuart_is_be;
> >>> +static u8 lpuart_reg_off;
> >>
> >> Global variables? That hardly works once you have two UARTs...
> >>
> > 
> > lpuart_reg_off is SoC specific and there's no two UART
> > with two different reg offset.
> > 
> >> Instead of adding a fixed offset to any write you could just add the
> >> offset to sport->port.membase...
> >>
> > 
> > That's intended as i don't want the changes to be too intrusive.
> > If adding offset in sport->port.xxx, then we have to change the basic
> > lpuart32_read/write API which is called through the whole driver.
> 
> Every lpuart32_write/read call passes port.membase, so if you offset
> port.membase when it is assigned in probe you should be fine not?
> 

Got your point now and that do seem better.
Thanks for the suggestion.
Will change in V2.

Regards
Dong Aisheng