[PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds
Geetha sowjanya
gakula at caviumnetworks.com
Fri May 5 05:08:04 PDT 2017
From: Linu Cherian <linu.cherian at cavium.com>
Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
1. Errata ID #74
SMMU register alias Page 1 is not implemented
2. Errata ID #126
SMMU doesnt support unique IRQ lines and also MSI for gerror,
eventq and cmdq-sync
The following patchset does software workaround for these two erratas.
This series is based on patchset.
https://www.spinics.net/lists/arm-kernel/msg578443.html
Changes from v1:
Since the use of MIDR register is rejected and SMMU_IIDR is broken on this
silicon, as suggested by Will Deacon modified the patches to use ThunderX2
SMMUv3 IORT model number to enable errata workaround.
Changes from v2:
Updated "Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt" document with
new SMMU option used to enable errata workaround.
Geetha Sowjanya (1):
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
Linu Cherian (6):
iommu/arm-smmu-v3: Introduce smmu option PAGE0_REGS_ONLY for ThunderX2
errata#74.
iommu/arm-smmu-v3: Do resource size checks based on SMMU option
PAGE0_REGS_ONLY
ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition.
iommu/arm-smmu-v3: For ACPI based device probing, set PAGE0_REGS_ONLY
option for ThunderX2 SMMUv3 implementations.
ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3
model
arm64: Documentation: Add Cavium ThunderX2 SMMUv3 erratas
Documentation/arm64/silicon-errata.txt | 2 +
drivers/acpi/arm64/iort.c | 10 ++-
drivers/iommu/arm-smmu-v3.c | 122 ++++++++++++++++++++++++++-------
include/acpi/actbl2.h | 2 +
4 files changed, 110 insertions(+), 26 deletions(-)
--
1.8.3.1
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