[PATCH 2/3] zte: clk: pd_bit is not 0 on zx296718

[Jun Nie]

2017-03-21 16:38 GMT+08:00 Shawn Guo <shawnguo at kernel.org>:
> From: Shawn Guo <shawn.guo at linaro.org>
>
> The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
> of postdiv2 field.  The consequence is that functions like hw_to_idx()
> and zx_pll_enable() will end up tampering the postdiv2 of the PLL.
>
> Let's fix it by defining pd_bit 0xff which is obviously invalid for a
> bit position and having PLL driver check the validity before operating
> on the bit.
>
> Signed-off-by: Shawn Guo <shawn.guo at linaro.org>

Reviewed-by: Jun Nie <jun.nie at linaro.org>