[PATCH v3 05/19] KVM: arm64: ITS: Implement vgic_its_has_attr_regs and attr_regs_access
Auger Eric
eric.auger at redhat.com
Wed Mar 22 07:15:05 PDT 2017
Andre,
On 20/03/2017 19:13, Andre Przywara wrote:
> Hi Eric,
>
> On 06/03/17 11:34, Eric Auger wrote:
>> This patch implements vgic_its_has_attr_regs and vgic_its_attr_regs_access
>> upon the MMIO framework. VGIC ITS KVM device KVM_DEV_ARM_VGIC_GRP_ITS_REGS
>> group becomes functional.
>>
>> At least GITS_CREADR requires to differentiate a guest write action from a
>> user access. As such let's introduce a new uaccess_its_write
>> vgic_register_region callback.
>>
>> Signed-off-by: Eric Auger <eric.auger at redhat.com>
>> ---
>> virt/kvm/arm/vgic/vgic-its.c | 74 ++++++++++++++++++++++++++++++++++++-------
>> virt/kvm/arm/vgic/vgic-mmio.h | 9 ++++--
>> 2 files changed, 69 insertions(+), 14 deletions(-)
>>
>> diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
>> index 43bb17e..e9c8f9f 100644
>> --- a/virt/kvm/arm/vgic/vgic-its.c
>> +++ b/virt/kvm/arm/vgic/vgic-its.c
>> @@ -1287,13 +1287,14 @@ static void vgic_mmio_write_its_baser(struct kvm *kvm,
>> *regptr = reg;
>> }
>>
>> -#define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
>> +#define REGISTER_ITS_DESC(off, rd, wr, uwr, length, acc) \
>> { \
>> .reg_offset = off, \
>> .len = length, \
>> .access_flags = acc, \
>> .its_read = rd, \
>> .its_write = wr, \
>> + .uaccess_its_write = uwr, \
>
> I was wondering if it would create less churn to keep this definition
> here (with .uaccess_its_write automatically becoming NULL), and then
> either open-code the one special case below or provide a second wrapper
> macro. But I guess either way is not really nice, so we could go with
> this approach here as well.
Agreed. I plan to introduce REGISTER_ITS_DESC_UACCESS in next patch instead.
>
>> }
>>
>> static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
>> @@ -1304,28 +1305,28 @@ static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
>>
>> static struct vgic_register_region its_registers[] = {
>> REGISTER_ITS_DESC(GITS_CTLR,
>> - vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
>> + vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, NULL, 4,
>> VGIC_ACCESS_32bit),
>> REGISTER_ITS_DESC(GITS_IIDR,
>> - vgic_mmio_read_its_iidr, its_mmio_write_wi, 4,
>> + vgic_mmio_read_its_iidr, its_mmio_write_wi, NULL, 4,
>> VGIC_ACCESS_32bit),
>> REGISTER_ITS_DESC(GITS_TYPER,
>> - vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
>> + vgic_mmio_read_its_typer, its_mmio_write_wi, NULL, 8,
>> VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>> REGISTER_ITS_DESC(GITS_CBASER,
>> - vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
>> + vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, NULL, 8,
>> VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>> REGISTER_ITS_DESC(GITS_CWRITER,
>> - vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
>> - VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>> + vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, NULL,
>> + 8, VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>> REGISTER_ITS_DESC(GITS_CREADR,
>> - vgic_mmio_read_its_creadr, its_mmio_write_wi, 8,
>> + vgic_mmio_read_its_creadr, its_mmio_write_wi, NULL, 8,
>> VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>> REGISTER_ITS_DESC(GITS_BASER,
>> - vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
>> + vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, NULL, 0x40,
>> VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
>> REGISTER_ITS_DESC(GITS_IDREGS_BASE,
>> - vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
>> + vgic_mmio_read_its_idregs, its_mmio_write_wi, NULL, 0x30,
>> VGIC_ACCESS_32bit),
>> };
>>
>> @@ -1448,14 +1449,63 @@ static void vgic_its_destroy(struct kvm_device *kvm_dev)
>> int vgic_its_has_attr_regs(struct kvm_device *dev,
>> struct kvm_device_attr *attr)
>> {
>> - return -ENXIO;
>> + const struct vgic_register_region *region;
>> + struct vgic_io_device iodev = {
>> + .regions = its_registers,
>> + .nr_regions = ARRAY_SIZE(its_registers),
>> + };
>> + gpa_t offset;
>> +
>> + offset = attr->attr;
>
> Those two can be on one line.
> But actually why not just put attr->attr below and save that variable at
> all?
done
>
>> +
>> + region = vgic_find_mmio_region(iodev.regions,
>> + iodev.nr_regions,
>> + offset);
>> + if (!region)
>> + return -ENXIO;
>
> Nit: empty line here?
done
>
>> + return 0;
>> }
>>
>> int vgic_its_attr_regs_access(struct kvm_device *dev,
>> struct kvm_device_attr *attr,
>> u64 *reg, bool is_write)
>> {
>> - return -ENXIO;
>> + const struct vgic_register_region *region;
>> + struct vgic_io_device iodev = {
>> + .regions = its_registers,
>> + .nr_regions = ARRAY_SIZE(its_registers),
>> + };
>> + struct vgic_its *its = dev->private;
>> + gpa_t addr, offset;
>> + unsigned int len;
>> +
>> + if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base))
>> + return -ENXIO;
>> +
>> + offset = attr->attr;
>> + if (offset & 0x7)
>> + return -EINVAL;
>
> Isn't this still breaking IIDR reads (a 32-bit register at offset 0x4)?
Hum yes it does. I will fix & test that. At the moment I was not
saving/restoring the IIDR but this is the plan now. Thanks for spotting
this.
>
>> +
>> + addr = its->vgic_its_base + offset;
>> +
>> + region = vgic_find_mmio_region(iodev.regions,
>> + iodev.nr_regions,
>> + offset);
>> + if (!region)
>> + return -ENXIO;
>> +
>> + len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4;
>
> Can you add a comment that states that we only support full register
> accesses via this interface (deviating from the spec which allows split
> accesses to 64-bit registers)? I think that's mentioned somewhere else
> (Documentation/...), but it avoids confusion for the casual reader here.
Added that comment.
>
> Also I am wondering if that way of using the pointer here for both 32-
> and 64-bit registers breaks on big endian? Or is it specified somewhere
> that this interface uses LE only?
Agreed, I used add vgic_data_mmio_bus_to_host and
vgic_data_host_to_mmio_bus handling.
Thanks
Eric
>
> The rest looks fine, thanks!
>
> Cheers,
> Andre.
>
>> + if (is_write) {
>> + if (region->uaccess_its_write)
>> + region->uaccess_its_write(dev->kvm, its, addr,
>> + len, *reg);
>> + else
>> + region->its_write(dev->kvm, its, addr, len, *reg);
>> + } else {
>> + *reg = region->its_read(dev->kvm, its, addr, len);
>> + }
>> + return 0;
>> }
>>
>> static int vgic_its_has_attr(struct kvm_device *dev,
>> diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h
>> index 055ad42..ad8a585 100644
>> --- a/virt/kvm/arm/vgic/vgic-mmio.h
>> +++ b/virt/kvm/arm/vgic/vgic-mmio.h
>> @@ -36,8 +36,13 @@ struct vgic_register_region {
>> };
>> unsigned long (*uaccess_read)(struct kvm_vcpu *vcpu, gpa_t addr,
>> unsigned int len);
>> - void (*uaccess_write)(struct kvm_vcpu *vcpu, gpa_t addr,
>> - unsigned int len, unsigned long val);
>> + union {
>> + void (*uaccess_write)(struct kvm_vcpu *vcpu, gpa_t addr,
>> + unsigned int len, unsigned long val);
>> + void (*uaccess_its_write)(struct kvm *kvm, struct vgic_its *its,
>> + gpa_t addr, unsigned int len,
>> + unsigned long val);
>> + };
>> };
>>
>> extern struct kvm_io_device_ops kvm_io_gic_ops;
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
More information about the linux-arm-kernel
mailing list