[PATCH 1/3] dt-bindings: imx-ocotp: add compatible string for i.MX7D/S
Peng Fan
peng.fan at nxp.com
Sun Mar 12 20:14:01 PDT 2017
> -----Original Message-----
> From: Srinivas Kandagatla [mailto:srinivas.kandagatla at linaro.org]
> Sent: Friday, March 03, 2017 6:12 PM
> To: Peng Fan <peng.fan at nxp.com>; shawnguo at kernel.org;
> maxime.ripard at free-electrons.com
> Cc: devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; van.freenix at gmail.com; Rob Herring
> <robh+dt at kernel.org>; Mark Rutland <mark.rutland at arm.com>
> Subject: Re: [PATCH 1/3] dt-bindings: imx-ocotp: add compatible string for
> i.MX7D/S
>
>
>
> On 01/03/17 06:40, Peng Fan wrote:
> > Add compatible string for i.MX7D/S
> >
> > Signed-off-by: Peng Fan <peng.fan at nxp.com>
> > Cc: Shawn Guo <shawnguo at kernel.org>
> > Cc: Srinivas Kandagatla <srinivas.kandagatla at linaro.org>
> > Cc: Maxime Ripard <maxime.ripard at free-electrons.com>
> > Cc: Rob Herring <robh+dt at kernel.org>
> > Cc: Mark Rutland <mark.rutland at arm.com>
> > ---
> > Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> Thanks for the patch, I will queue both nvmem driver changes and bindings
> changes, via Greg's chars-misc tree.
> But the DT changes have to go via arm-soc tree.
Thanks, Srini.
Shawn may take the DT changes, if it is ok.
Thanks,
Peng.
>
> Thanks,
> srini
> > diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > index 966a72e..bbde2e4 100644
> > --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > @@ -9,6 +9,7 @@ Required properties:
> > "fsl,imx6sl-ocotp" (i.MX6SL), or
> > "fsl,imx6sx-ocotp" (i.MX6SX),
> > "fsl,imx6ul-ocotp" (i.MX6UL),
> > + "fsl,imx7d-ocotp" (i.MX7D/S),
> > followed by "syscon".
> > - reg: Should contain the register base and length.
> > - clocks: Should contain a phandle pointing to the gated peripheral clock.
> >
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