L2 cache management question

Bijal Shah (bishah) bishah at cisco.com
Wed Mar 8 03:44:12 PST 2017

Hi all,

I hope this is this the right mailer for this question.

I've been looking into an issue on an ARM platform which seems to revolve around the way the L2 cache is managed by the kernel.

Looking at l2x0_cache.c file in the arch/arm/mm directory, I see a common pattern for an address range flush where if the address range is larger than the cache size, a flush_all is called almost without question. Is there any specific reason for this? Asking for the project I'm working on, as the address ranges may contain very few if any dirty lines, and a flush_all is expensive and locks out other CPUs while it is going on.


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