[PATCH v2 3/5] arm64: dts: Add ufs dts node

[Bu Tao]

arm64: dts: add ufs node for hi3660

Signed-off-by: Bu Tao <butao at hisilicon.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts |  9 +++++++++
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi         | 19 +++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 186251ffc6b2..5dbe642f3c66 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -32,3 +32,12 @@
 &uart5 {
 	status = "okay";
 };
+
+&ufs {
+	ufs-hi3660-use-rate-B;
+	ufs-hi3660-broken-fastauto;
+	ufs-hi3660-use-HS-GEAR3;
+	ufs-hi3660-broken-clk-gate-bypass;
+	reset-gpio = <&gpio18 1 0>;
+	status = "okay";
+}
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..e688fdb0a939 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -141,6 +141,25 @@
 		#size-cells = <2>;
 		ranges;
 
+		ufs: ufs at ff3b0000 {
+			compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
+			/* 0: HCI standard */
+			/* 1: UFS SYS CTRL */
+			reg = <0x0 0xff3b0000 0x0 0x1000>,
+				<0x0 0xff3b1000 0x0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+			clock-names = "clk_ref", "clk_phy";
+			freq-table-hz = <0 0>, <0 0>;
+			/* offset: 0x84; bit: 12 */
+			/* offset: 0x84; bit: 7  */
+			resets = <&crg_rst 0x84 12>,
+				<&crg_rst 0x84 7>;
+			reset-names = "rst", "assert";
+		};
+
 		fixed_uart5: fixed_19_2M {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-- 
2.11.GIT