[PATCH 03/12] coresight: Extend the PIDR mask to cover relevant bits in PIDR2

[Suzuki K Poulose]

On 13/06/17 18:53, Mathieu Poirier wrote:
> On Mon, Jun 12, 2017 at 03:36:42PM +0100, Suzuki K Poulose wrote:
>> As per coresight standards, PIDR2 register has the following format :
>>
>>  [2-0]	- JEP106_bits6to4
>>  [3]	- JEDEC, designer ID is specified by JEDEC.
>>
>> However some of the drivers only use mask of 0x3 for the PIDR2 leaving
>> bits [3-2] unchecked, which could potentially match the component for
>> a different device altogether. This patch fixes the mask and the
>> corresponding id bits for the existing devices.
>>
>> Cc: Mathieu Poirier <mathieu.poirier at linaro.org>
>> Cc: Linus Walleij <linus.walleij at linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>
>> ---
>> I have not touched the TPIU ids for Ux500 (see commit: 4339b699),
>> as I don't have a platform to fix/correct the ids.
>> ---
>>  drivers/hwtracing/coresight/coresight-funnel.c          | 4 ++--
>>  drivers/hwtracing/coresight/coresight-replicator-qcom.c | 4 ++--
>>  drivers/hwtracing/coresight/coresight-stm.c             | 8 ++++----
>>  drivers/hwtracing/coresight/coresight-tmc.c             | 4 ++--
>>  drivers/hwtracing/coresight/coresight-tpiu.c            | 4 ++--
>
> Any reason for not adding ETMv3 to the list?  From what I see in the
> documentation bit [2-0] need to 0b011 and the JEDEC bit is always 1.

I don't have a platform to test it easily. Hence the exclusion. Same for
etbv10.


Suzuki