[PATCH v2] clk: fractional-divider: fix up the fractional clk's jitter

[Heiko Stuebner]

Hi Elaine,

Am Freitag, 7. Juli 2017, 10:52:23 CEST schrieb Elaine Zhang:
> add clk_fractional_divider_special_ops for rockchip specific requirements,
> fractional divider must set that denominator is 20 times larger than
> numerator to generate precise clock frequency.
> Otherwise the CLK jitter is very big, poor quality of the clock signal.
> 
> RK document description:
> 3.1.9  Fractional divider usage
> To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by
> fractional divider. Generally you must set that denominator is 20 times
> larger than numerator to generate precise clock frequency. So the
> fractional divider applies only to generate low frequency clock like
> I2S, UART.igned-off-by: Elaine Zhang <zhangqing at rock-chips.com>
> 
> Signed-off-by: Elaine Zhang <zhangqing at rock-chips.com>
> ---
>  drivers/clk/clk-fractional-divider.c | 32 ++++++++++++++++++++++++++++++++
>  drivers/clk/rockchip/clk.c           |  2 +-
>  include/linux/clk-provider.h         |  1 +
>  3 files changed, 34 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
> index aab904618eb6..3107b33327f9 100644
> --- a/drivers/clk/clk-fractional-divider.c
> +++ b/drivers/clk/clk-fractional-divider.c
> @@ -158,6 +158,38 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
>  }
>  EXPORT_SYMBOL_GPL(clk_hw_register_fractional_divider);
>  
> +static long clk_fd_round_rate_special(struct clk_hw *hw, unsigned long rate,
> +				      unsigned long *parent_rate)
> +{

this obviously still encodes Rockchip-specific things into the generic
fractional-divider driver. And it's of course only special for Rockchip
fractional dividers and will end it chaos if every implementation wants
to add a "special" function there.

Did you have a look at the patch I added to the last mail (for real this time)?


Heiko