[PATCH v4 2/4] arm64: Work around Falkor erratum 1003

[Christopher Covington]

Hi Mark,

On 01/30/2017 05:56 AM, Mark Rutland wrote:
> Hi,
> 
> On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote:
>> On 01/27/2017 09:38 AM, Mark Rutland wrote:
>>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
> 
>>>> Replacing the above sequence with the one below will ensure that no TLB
>>>> entries with an incorrect ASID are used by software.
>>>>
>>>>   write reserved value to TTBRx_EL1[ASID]
>>>>   ISB
>>>>   write new value to TTBRx_EL1[BADDR]
>>>>   ISB
>>>>   write new value to TTBRx_EL1[ASID]
>>>>   ISB
>>>>
>>>> When the above sequence is used, page table entries using the new BADDR
>>>> value may still be incorrectly allocated into the TLB using the reserved
>>>> ASID. Yet this will not reduce functionality, since TLB entries incorrectly
>>>> tagged with the reserved ASID will never be hit by a later instruction.
>>>
>>> I agree that there should be no explicit accesses to the VAs for these
>>> entries. So tasks should not see erroneous VAs, and we shouldn't see
>>> synchronous TLB conflict aborts.
>>>
>>> Regardless, can this allow conflicting TLB entries to be allocated to
>>> the reserved ASID? e.g. if one task has a 4K mapping at a given VA, and
>>> another has a 2M mapping which covers that VA, can both be allocated
>>> into the TLBs under the reserved ASID?
>>>
>>> Can that have any effect on asynchronous TLB lookups or page table
>>> walks, e.g. for speculated accesses?
>>
>> A speculative access that inserts an entry into the TLB could
>> possibly find the conflict but will not signal it. Does that answer
>> your question?
> 
> Yes!
> 
> The other case I was worried about was intermediate caching. I take it
> the values in TLBs are not used as part of subsequent page table walks?
> 
> If so, the above sounds fine to me.
> 
> Otherwise, we'll need additional TLB maintenance.

Errant TLB entries will not be used for any legitimate subsequent page
table walks.

I have some minor changes which I'll send as v5 based on
kernel/git/arm64/linux.git for-next/core.

Thanks,
Cov

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