[PATCH v2 02/10] clk: ccu-sun8i-a33: Add CLK_SET_RATE_PARENT to ac-dig

[Mylene Josserand]

Hi,

On 17/01/2017 17:44, Maxime Ripard wrote:
> Hi,
>
> On Tue, Jan 17, 2017 at 03:02:22PM +0100, Mylène Josserand wrote:
>> The audio DAI needs to set the clock rates of the ac-dig clock.
>> To make it possible, the parent PLL audio clock rates should
>> also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.
>>
>> Signed-off-by: Mylène Josserand <mylene.josserand at free-electrons.com>
>
> Please make sure to look at the prefixes usually used in the commit
> titles of the area you're working on. In this case that would have
> been "clk: sunxi-ng:". I fixed it, and applied.

Okay, I will pay more attention to prefixes for commit titles for next 
times.

Thank you !

-- 
Mylène Josserand, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com