[PATCH 2/3] ARM: dts: r8a7743: Add CMT SoC specific support

Simon Horman horms at verge.net.au
Wed Dec 13 00:38:29 PST 2017


On Tue, Dec 12, 2017 at 06:49:38PM +0000, Fabrizio Castro wrote:
> Add CMT[01] support to SoC DT.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro at bp.renesas.com>
> Reviewed-by: Biju Das <biju.das at bp.renesas.com>
> ---
>  arch/arm/boot/dts/r8a7743.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)

I was expecting the cmt nodes to be "disabled" in the SoC file
and then enabled selectively in board files. Am I missing something?

Otherwise this patch looks good to me.

> diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
> index 59860c8..0e2834a 100644
> --- a/arch/arm/boot/dts/r8a7743.dtsi
> +++ b/arch/arm/boot/dts/r8a7743.dtsi
> @@ -262,6 +262,36 @@
>  						  IRQ_TYPE_LEVEL_LOW)>;
>  		};
>  
> +		cmt0: timer at ffca0000 {
> +			compatible = "renesas,r8a7743-cmt0",
> +				     "renesas,rcar-gen2-cmt0";
> +			reg = <0 0xffca0000 0 0x1004>;
> +			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 124>;
> +			clock-names = "fck";
> +			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
> +			resets = <&cpg 124>;
> +		};
> +
> +		cmt1: timer at e6130000 {
> +			compatible = "renesas,r8a7743-cmt1",
> +				     "renesas,rcar-gen2-cmt1";
> +			reg = <0 0xe6130000 0 0x1004>;
> +			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 329>;
> +			clock-names = "fck";
> +			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
> +			resets = <&cpg 329>;
> +		};
> +
>  		cpg: clock-controller at e6150000 {
>  			compatible = "renesas,r8a7743-cpg-mssr";
>  			reg = <0 0xe6150000 0 0x1000>;
> -- 
> 2.7.4
> 



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