[PATCH v5 2/2] PCI: quirks: Fix ThunderX2 dma alias handling
bhelgaas at google.com
Thu Apr 20 09:20:38 EDT 2017
On Wed, Apr 19, 2017 at 7:25 PM, Jon Masters <jcm at redhat.com> wrote:
> One additional footnote. I spent a bunch of time recently on my personal
> Xeon systems walking through the PCIe topology and aligning on how to
> advise the ARM server community proceed going forward. If you look at
> how Intel vs AMD handle their host bridges for example, you'll see two
> very different approaches to the case of cross-socket PCIe.
As a learning opportunity for me, can you share "lspci -vv" examples
that show this Intel vs AMD difference? Maybe the ACPI host bridge
descriptions from dmesg are relevant too?
> But my
> operating assumption is that anything longer term which looks boring and
> x86 enough is probably fine from an ARM server point of view.
That sounds pretty safe to me.
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