[PATCH v3 06/32] avr32: include default ioremap_nopost() implementation

Lorenzo Pieralisi lorenzo.pieralisi at arm.com
Tue Apr 11 08:28:46 EDT 2017

The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting")
mandate non-posted configuration transactions. As further highlighted in
the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the
Enhanced Configuration Access Mechanism"), through ECAM and
ECAM-derivative configuration mechanism, the memory mapped transactions
from the host CPU into Configuration Requests on the PCI express fabric
may create ordering problems for software because writes to memory
address are typically posted transactions (unless the architecture can
enforce through virtual address mapping non-posted write transactions
behaviour) but writes to Configuration Space are not posted on the PCI
express fabric.

Include the asm-generic ioremap_nopost() implementation (currently
falling back to ioremap_nocache()) to provide a non-posted writes
ioremap interface to kernel subsystems.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
Cc: Bjorn Helgaas <bhelgaas at google.com>
Cc: Hans-Christian Egtvedt <egtvedt at samfundet.no>
Cc: Haavard Skinnemoen <hskinnemoen at gmail.com>
 arch/avr32/include/asm/io.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h
index f855646..b2ff522 100644
--- a/arch/avr32/include/asm/io.h
+++ b/arch/avr32/include/asm/io.h
@@ -298,6 +298,7 @@ extern void __iounmap(void __iomem *addr);
 #define ioremap_wc ioremap_nocache
 #define ioremap_wt ioremap_nocache
 #define ioremap_uc ioremap_nocache
+#include <asm-generic/ioremap-nopost.h>
 #define cached(addr) P1SEGADDR(addr)
 #define uncached(addr) P2SEGADDR(addr)

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